| Topic: |
Science > Physics |
| User: |
"Andrew" |
| Date: |
05 May 2004 11:11:54 AM |
| Object: |
Scaling beyond 130nm dead or alive? |
In two related articles from www.physnews.com they seem to claim completely
different things:
One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
65 nm" http://www.physorg.com/news52.htm
And another "Scaling dead at 130-nm, says IBM technologist"
http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
I'm really confused!!! One say we will never go over 90nm, and at the same
time Intel spends a lot of money to build a factory for 65nm!
Your comments.
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| User: "Uncle Al" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
05 May 2004 02:19:22 PM |
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Andrew wrote:
In two related articles from www.physnews.com they seem to claim completely
different things:
One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
65 nm" http://www.physorg.com/news52.htm
And another "Scaling dead at 130-nm, says IBM technologist"
http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
I'm really confused!!! One say we will never go over 90nm, and at the same
time Intel spends a lot of money to build a factory for 65nm!
Your comments.
90 nm architecture is in commercial production. Pentiums pass 4 GHz
for Christmas. Don't get all excited; Intel CPUs are *****. AMD's
Opterons (and Athlon-FX with smaller caches) are simultaneous 32-bit
and 64-bit chips with 100% x86 compatiblity. Everything you have is
already obsolete. It's only a matter of time unitl Win-64 and the
Blue Screen of Death breaks Mach 1.
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
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| User: "Fleetie" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
15 May 2004 01:58:27 PM |
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"Uncle Al" <UncleAl0@hate.spam.net> wrote
90 nm architecture is in commercial production. Pentiums pass 4 GHz
for Christmas. Don't get all excited; Intel CPUs are *****. AMD's
Opterons (and Athlon-FX with smaller caches) are simultaneous 32-bit
and 64-bit chips with 100% x86 compatiblity. Everything you have is
already obsolete. It's only a matter of time unitl Win-64 and the
Blue Screen of Death breaks Mach 1.
Ah, I haven't been here in this newsgroup for over a year, I think.
But it's great to see Dr. Schwartz is still here putting out the
word!
And yes, it's appalling how bad Intel CPUs are at FP. I wrote a
little noddy benchmark proggy just after I got this Athlon 2000
a couple of years ago. Very roughly it whooped an equivalently-
clocked Pentium by about a factor of THREE! Even writing this I
have difficulty believing that, but such is my memory. In a way,
I hope I'm wrong about it.
"How long do we wait until 64 bit and Windows are mature enough to be
worth buying?", I wonder.
Martin
--
M.A.Poyser Tel.: 07967 110890
Manchester, U.K. http://www.fleetie.demon.co.uk
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| User: "Mark Thorson" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
15 May 2004 03:54:29 PM |
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Fleetie wrote:
And yes, it's appalling how bad Intel CPUs are at FP. I wrote a
little noddy benchmark proggy just after I got this Athlon 2000
a couple of years ago. Very roughly it whooped an equivalently-
clocked Pentium by about a factor of THREE! Even writing this I
have difficulty believing that, but such is my memory. In a way,
I hope I'm wrong about it.
This reminds me of someone I knew who bought a new machine.
He wrote a little benchmark and set it for a miilion iterations.
POW! It came right back. "Gee, that's pretty fast," he thought.
(This was in the days of 386 machines.)
Then he set it for 10 million iterations. POW! It came right back.
Now he knew something was wrong. He popped the object code into the
debugger, and he discovered his compiler had realized no products of the
loop were being examined, and it removed the loop from his program.
Perhaps you are observing a difference in the compilers used
for Intel vs. AMD machines?
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| User: "Uncle Al" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
15 May 2004 05:28:10 PM |
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Mark Thorson wrote:
Fleetie wrote:
And yes, it's appalling how bad Intel CPUs are at FP. I wrote a
little noddy benchmark proggy just after I got this Athlon 2000
a couple of years ago. Very roughly it whooped an equivalently-
clocked Pentium by about a factor of THREE! Even writing this I
have difficulty believing that, but such is my memory. In a way,
I hope I'm wrong about it.
This reminds me of someone I knew who bought a new machine.
He wrote a little benchmark and set it for a miilion iterations.
POW! It came right back. "Gee, that's pretty fast," he thought.
(This was in the days of 386 machines.)
Then he set it for 10 million iterations. POW! It came right back.
Now he knew something was wrong. He popped the object code into the
debugger, and he discovered his compiler had realized no products of the
loop were being examined, and it removed the loop from his program.
Perhaps you are observing a difference in the compilers used
for Intel vs. AMD machines?
MS C++ compilers (and apparently other Mickeycrap compilers)
automatically default long_double_precision in source code to
double_precision executables. No flags, no warnings, no
documentation. This gives a considerable speed advantage over
properly compiled source code, albeit with some sacrifice of meaning
(all of it) in the data.
In running parity divergence calculations on large lattices
(10^12-10^18 atoms) we found a single Intel 3.2 GHz Xeon throughput
40-60% less/clock cycle than a single 2.8 GHz AMD Opteron-244, both
running under Linux. Running parallel, we had 16 Opteron-848s pulling
an honest 4+ GFLOPS each continuous (40 days of donated access
overall), plus incredible bursts when it was lattice growth only. The
G5 processor farm at Virginia Tech probably would have done better,
but it wasn't free. You'd need some dozens of Xeons in parallel to
compete. Xeons have tiny CPU caches, memory controller off CPU, and
no coherent HyperTransport. Running Xeons in parallel is a bad joke.
Hint: If you are doing serious crunching, it isn't the compiler.
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
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| User: "The Ghost In The Machine" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
06 May 2004 11:08:48 AM |
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In sci.physics, Uncle Al
<UncleAl0@hate.spam.net>
wrote
on 5 May 2004 19:19:22 GMT
<c7benq0q9p@enews4.newsguy.com>:
Andrew wrote:
In two related articles from www.physnews.com they seem to claim completely
different things:
One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
65 nm" http://www.physorg.com/news52.htm
And another "Scaling dead at 130-nm, says IBM technologist"
http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
I'm really confused!!! One say we will never go over 90nm, and at the same
time Intel spends a lot of money to build a factory for 65nm!
Your comments.
90 nm architecture is in commercial production. Pentiums pass 4 GHz
for Christmas. Don't get all excited; Intel CPUs are *****. AMD's
Opterons (and Athlon-FX with smaller caches) are simultaneous 32-bit
and 64-bit chips with 100% x86 compatiblity. Everything you have is
already obsolete. It's only a matter of time unitl Win-64 and the
Blue Screen of Death breaks Mach 1.
I think the viruses/worms/malware already did... :-)
When I first started employment I remember cleaning tapeups.
I'd be surprised if there are any left.
[ Sci.nanotech Moderator's Note: Since this has gone off-topic for sci.nanotech
the followup-to header has been set to exclude said group. -JimL ]
--
#191, -- insert random "technological innovation" here
It's still legal to go .sigless.
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| User: "" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
07 May 2004 10:43:39 PM |
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Maybe not so obvious from the eye catching title but the EE Times text
moderates it a little to say that "_traditional_ scaling" is dead. So
it depends on what you mean traditional scaling.
What do we mean by scaling anyways? Dennard from IBM set up some
"rules" way back in the 20th century saying CMOS designs can be
"scaled" by simultaneous and correlated reduction in things like oxide
thickness, length, width, supply voltages, junction depth, and doping.
The idea being that you can take any CMOS VLSI chip, multiply
everything by the magic scaling number, run it through newer tools and
{POOF} like a cookie recipe: you get the same design at lower cost
per chip. The magic number is traditionally set at 71% shrink (e.g.
65nm/90nm) per generation to area shrinks by half a la Moore's law.
Truth is it doesn't quite worked out quite so neatly. And each
generation it's getting harder to pretend that "scaling" applies at
all. Parameters "scale" unevenly -- at "65nm" maybe only one
parameter is actually equal or less than 65nm -- in spite of what the
"rules" say it should be. I get the sense that the IBM guy is talking
about these rules being dead rather than CMOS being dead.
Just FYI, these 90/65/45 nm "node" values are becoming something of a
marketing gimic... like CPU clock speed. For example read:
http://www.eet.com/showArticle.jhtml?articleID=18311172
But better believe that if Intel spends $2B, there is still some
economic sensibility to it. *Something(s)* about the new process will
be 65-ish nm or smaller. To make economic sense it will be also be
faster or cheaper or more complex or some other definition of
"better". In the end, the rules that count {for this scope of
discussion anyways} are economic rather than physical.
-Lee
"Andrew" <andrew_zi@yahoo.com> wrote in message
news:<c7b3oa06b8@enews3.newsguy.com>...
In two related articles from www.physnews.com they seem to claim completely
different things:
One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
65 nm" http://www.physorg.com/news52.htm
And another "Scaling dead at 130-nm, says IBM technologist"
http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
I'm really confused!!! One say we will never go over 90nm, and at the same
time Intel spends a lot of money to build a factory for 65nm!
Your comments.
.
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| User: "Andrew" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
08 May 2004 12:03:01 PM |
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<lee_posts04@yahoo.com> wrote in message
news:c7hl1b023rd@enews2.newsguy.com...
Truth is it doesn't quite worked out quite so neatly. And each
generation it's getting harder to pretend that "scaling" applies at
all. Parameters "scale" unevenly -- at "65nm" maybe only one
parameter is actually equal or less than 65nm -- in spite of what the
"rules" say it should be. I get the sense that the IBM guy is talking
about these rules being dead rather than CMOS being dead.
This is exactly my question. Are those 65 or 45 nm real CMOS dimensions or
that are fake "equivalent" numbers, that only represent higher computer
power?
If second is the case, then some definitions for "equivalency" must already
be revealed, but I've never heard about that yet.
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| User: "John Larkin" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
06 May 2004 09:59:59 PM |
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On 5 May 2004 16:11:54 GMT, "Andrew" <andrew_zi@yahoo.com> wrote:
In two related articles from www.physnews.com they seem to claim completely
different things:
One is here "Intel Begins $2 Billion Conversion Of Arizona Factory to Start
65 nm" http://www.physorg.com/news52.htm
And another "Scaling dead at 130-nm, says IBM technologist"
http://eetimes.com/semi/news/showArticle.jhtml?articleId=19502091
I'm really confused!!! One say we will never go over 90nm, and at the same
time Intel spends a lot of money to build a factory for 65nm!
Your comments.
I think that the point is that simple scaling - "die shrinks" - are no
longer feasible, as they were in the past. Time was, when you got
better process resolution, you could just crank the optics to reduce
an existing mask set. The physics has changed nonlinearly, so new
device designs are needed to exploit sub-100 nm features. Several
people have 90 nm stuff in production, but it ain't easy. At 50 nm and
down, whole new devices, finfets or something, will be needed.
John
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| User: "Mark Thorson" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
07 May 2004 10:57:05 AM |
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John Larkin wrote:
I think that the point is that simple scaling - "die shrinks" - are
no longer feasible, as they were in the past.
Not to mention that smaller feature size is not the major driver of
so-called "Moore's Law". Crystal defect density has been the major
driver in recent years. Moore's Law says the number of transistors
per device doubles every two years. Scaling down the linear dimension
by 2 increases the transistor density by 4, but that's hard to do.
Decreasing the defect density allows you to build larger chips
that can be manufactured with acceptable yield. Feature size
may hit a law-of-physics stumbling block, but that will not happen
to advances in reducing defect density. Until we have single chips
the size of dinner plates, there will be room for improvement based
on defect density alone, which is the major driver for Moore's Law.
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| User: "Richard Henry" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
07 May 2004 04:21:13 PM |
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"Mark Thorson" <nospam@sonic.net> wrote in message
news:c7gbkh026l9@enews4.newsguy.com...
Moore's Law says the number of transistors
per device doubles every two years.
Various sources cite 1 year, 18 months or two years, and target number of
devices, "complexity", power consumption and reliability as the factors and
objectives.
http://www.google.com/search?sourceid=navclient&ie=UTF-8&oe=UTF-8&q=moore%27s+law
Moore's paper appeared in 1965, when he was with Fairchild Electronics, in
Electronics Magazine, when that was still a meaningful publication.
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| User: "Mark Thorson" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
08 May 2004 12:03:09 PM |
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Richard Henry wrote:
Moore's paper appeared in 1965, when he was with Fairchild Electronics,
in Electronics Magazine, when that was still a meaningful publication.
That's Fairchild Camera and Instrument, not Fairchild Electronics.
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| User: "Phil Hobbs" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
07 May 2004 04:21:29 PM |
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Mark Thorson wrote:
John Larkin wrote:
I think that the point is that simple scaling - "die shrinks" - are
no longer feasible, as they were in the past.
Not to mention that smaller feature size is not the major driver of
so-called "Moore's Law". Crystal defect density has been the major
driver in recent years. Moore's Law says the number of transistors
per device doubles every two years. Scaling down the linear dimension
by 2 increases the transistor density by 4, but that's hard to do.
Decreasing the defect density allows you to build larger chips
that can be manufactured with acceptable yield. Feature size
may hit a law-of-physics stumbling block, but that will not happen
to advances in reducing defect density. Until we have single chips
the size of dinner plates, there will be room for improvement based
on defect density alone, which is the major driver for Moore's Law.
Except that you can't cool them, and they'll tear the solder balls right out
of the module as they heat up. Maybe we can use elastic silicon ;-)
Cheers,
Phil Hobbs
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| User: "Gordon D. Pusch" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
07 May 2004 10:21:19 PM |
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Phil Hobbs <pcdhSpamMeSenseless@us.ibm.com> writes:
Mark Thorson wrote:
John Larkin wrote:
I think that the point is that simple scaling - "die shrinks" - are
no longer feasible, as they were in the past.
Not to mention that smaller feature size is not the major driver of
so-called "Moore's Law". Crystal defect density has been the major
driver in recent years. Moore's Law says the number of transistors
per device doubles every two years. Scaling down the linear dimension
by 2 increases the transistor density by 4, but that's hard to do.
Decreasing the defect density allows you to build larger chips
that can be manufactured with acceptable yield. Feature size
may hit a law-of-physics stumbling block, but that will not happen
to advances in reducing defect density. Until we have single chips
the size of dinner plates, there will be room for improvement based
on defect density alone, which is the major driver for Moore's Law.
Except that you can't cool them, and they'll tear the solder balls right
out of the module as they heat up. Maybe we can use elastic silicon ;-)
Long before we reach that point, we will probably be forced to transition
from dissipative logic to reversible logic. (The only computing operations
that _have_ to generate heat are I/O operations.)
Nanotech will probably also require reversible logic, in order to avoid
cooking itself...
For links to reversible computing and its relation to nanotechnology,
see <http://www.zyvex.com/nanotech/reversible.html>.
For one group that has performed some excellent experimental research into
reversible computing, including building some prototype devices, see:
<http://www.elis.rug.ac.be/ELISgroups/solar/projects/computer.html>.
-- Gordon D. Pusch
perl -e '$_ = "gdpusch\@NO.xnet.SPAM.com\n"; s/NO\.//; s/SPAM\.//; print;'
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| User: "Phil Hobbs" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
08 May 2004 01:00:23 AM |
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Gordon D. Pusch wrote:
Phil Hobbs <pcdhSpamMeSenseless@us.ibm.com> writes:
Mark Thorson wrote:
John Larkin wrote:
I think that the point is that simple scaling - "die shrinks" - are
no longer feasible, as they were in the past.
Not to mention that smaller feature size is not the major driver of
so-called "Moore's Law". Crystal defect density has been the major
driver in recent years. Moore's Law says the number of transistors
per device doubles every two years. Scaling down the linear dimension
by 2 increases the transistor density by 4, but that's hard to do.
Decreasing the defect density allows you to build larger chips
that can be manufactured with acceptable yield. Feature size
may hit a law-of-physics stumbling block, but that will not happen
to advances in reducing defect density. Until we have single chips
the size of dinner plates, there will be room for improvement based
on defect density alone, which is the major driver for Moore's Law.
Except that you can't cool them, and they'll tear the solder balls right
out of the module as they heat up. Maybe we can use elastic silicon ;-)
Long before we reach that point, we will probably be forced to transition
from dissipative logic to reversible logic. (The only computing operations
that _have_ to generate heat are I/O operations.)
Nanotech will probably also require reversible logic, in order to avoid
cooking itself...
For links to reversible computing and its relation to nanotechnology,
see <http://www.zyvex.com/nanotech/reversible.html>.
For one group that has performed some excellent experimental research into
reversible computing, including building some prototype devices, see:
<http://www.elis.rug.ac.be/ELISgroups/solar/projects/computer.html>.
-- Gordon D. Pusch
perl -e '$_ = "gdpusch\@NO.xnet.SPAM.com\n"; s/NO\.//; s/SPAM\.//; print;'
Yeah, I know--I work in the building where reversible computing was invented,
many moons ago. If CMOS is really running into a brick wall, though,
there'll be enough blood on the landscape that we may all be out of work
before reversible computing becomes practical (if that ever happens).
There's a _lot_ of work going on just now on how to cool next-generation CMOS
without circulating water right to the chip level. People are even talking
about cutting channels into the back surface of the chips, to run cooling
water. I don't think things are quite that desperate, but we're clearly in a
new ballgame.
Cheers,
Phil Hobbs
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| User: "John Larkin" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
08 May 2004 04:59:21 PM |
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On 8 May 2004 06:00:23 GMT, Phil Hobbs
<pcdhSpamMeSenseless@us.ibm.com> wrote:
Yeah, I know--I work in the building where reversible computing was invented,
many moons ago. If CMOS is really running into a brick wall, though,
there'll be enough blood on the landscape that we may all be out of work
before reversible computing becomes practical (if that ever happens).
There's a _lot_ of work going on just now on how to cool next-generation CMOS
without circulating water right to the chip level. People are even talking
about cutting channels into the back surface of the chips, to run cooling
water. I don't think things are quite that desperate, but we're clearly in a
new ballgame.
Cheers,
Phil Hobbs
I wish somebody would start mass-producing cheap bulk monocrystalline
diamond, preferably the single-isotope kind.
John
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| User: "Uncle Al" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
08 May 2004 09:32:29 PM |
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John Larkin wrote:
On 8 May 2004 06:00:23 GMT, Phil Hobbs
<pcdhSpamMeSenseless@us.ibm.com> wrote:
Yeah, I know--I work in the building where reversible computing was invented,
many moons ago. If CMOS is really running into a brick wall, though,
there'll be enough blood on the landscape that we may all be out of work
before reversible computing becomes practical (if that ever happens).
There's a _lot_ of work going on just now on how to cool next-generation CMOS
without circulating water right to the chip level. People are even talking
about cutting channels into the back surface of the chips, to run cooling
water. I don't think things are quite that desperate, but we're clearly in a
new ballgame.
I wish somebody would start mass-producing cheap bulk monocrystalline
diamond, preferably the single-isotope kind.
Kilo crystals? We're working on it. 6 months or never.
Machinist, "Hell, I can drill through the old reactor head. Keep the
new blank."
The old head started as T-316SS that had been heated to 800+ C for a
total of nearly 200 hours. It contained molten Devil Solvent all that
time. It's an inch+ thick, too. The head wasn't barrier-plated.
What could happen to an inch of 316SS? We ruined TiN-coated drill
bits trying to get into it.
Machinist, "Do you still have the blank head?"
We had a big pure copper pipe endcap as spill containment in the
reactor, for the inner pot that held Devil Solvent. Copper shatters
like glass after Devil Solvent, which is no big deal if it sits
there. Turns out Devil Solvent also vapor-transports at temp, so
spill containment is moot. The copper endcap expanded 8% in all
dimensions. We can't imagine what is in there with the metal. It
still looks like its mates, but it's bigger.
The chemistry and now the engineering seem to be under control. We're
going for a third and final set of runs. Chemical precursor
progressively reacts to elemental carbon under local energetic
conditions. Diamond persists in molten Devil Solvent, graphite
furiously (oh yes indeed - no densified graphite containment) erodes
away. Boron doping to give Type IIb blue diamond that phosphoresces
red for 60-90 seconds after 254 nm UV excitation. If we make diamond
it we'll find it - like everything else we do, working in the dark.
--
Uncle Al
http://www.mazepath.com/uncleal/qz.pdf
http://www.mazepath.com/uncleal/eotvos.htm
(Do something naughty to physics)
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| User: "John Larkin" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
09 May 2004 02:20:44 PM |
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On 9 May 2004 02:32:29 GMT, Uncle Al <UncleAl0@hate.spam.net> wrote:
I wish somebody would start mass-producing cheap bulk monocrystalline
diamond, preferably the single-isotope kind.
Kilo crystals? We're working on it. 6 months or never.
Machinist, "Hell, I can drill through the old reactor head. Keep the
new blank."
The old head started as T-316SS that had been heated to 800+ C for a
total of nearly 200 hours. It contained molten Devil Solvent all that
time. It's an inch+ thick, too. The head wasn't barrier-plated.
What could happen to an inch of 316SS? We ruined TiN-coated drill
bits trying to get into it.
Machinist, "Do you still have the blank head?"
We had a big pure copper pipe endcap as spill containment in the
reactor, for the inner pot that held Devil Solvent. Copper shatters
like glass after Devil Solvent, which is no big deal if it sits
there. Turns out Devil Solvent also vapor-transports at temp, so
spill containment is moot. The copper endcap expanded 8% in all
dimensions. We can't imagine what is in there with the metal. It
still looks like its mates, but it's bigger.
The chemistry and now the engineering seem to be under control. We're
going for a third and final set of runs. Chemical precursor
progressively reacts to elemental carbon under local energetic
conditions. Diamond persists in molten Devil Solvent, graphite
furiously (oh yes indeed - no densified graphite containment) erodes
away. Boron doping to give Type IIb blue diamond that phosphoresces
red for 60-90 seconds after 254 nm UV excitation. If we make diamond
it we'll find it - like everything else we do, working in the dark.
Once we do have slabs of diamond in the McMaster catalog, how will we
machine it? For semiconductor heat spreaders, all we'd really need is
little blocks of the stuff, maybe no holes at all, so we could buy
standard sizes. But what's a good way to, say, machine holes in the
stuff? I did a motion-control thing (a magnetic field mapper) on a big
slab of granite, and that was bad enough.
Isotopically pure diamond would have a thermal conductivity/dielectric
constant ratio about 400:1 better than, say, BeO; makes me salivate
just thinking about it.
Let me know when you have samples available.
John
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| User: "Uncle Al" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
09 May 2004 06:59:08 PM |
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John Larkin wrote:
On 9 May 2004 02:32:29 GMT, Uncle Al <UncleAl0@hate.spam.net> wrote:
I wish somebody would start mass-producing cheap bulk monocrystalline
diamond, preferably the single-isotope kind.
Kilo crystals? We're working on it. 6 months or never.
[snip]
Once we do have slabs of diamond in the McMaster catalog, how will we
machine it?
Laser it.
For semiconductor heat spreaders, all we'd really need is
little blocks of the stuff, maybe no holes at all, so we could buy
standard sizes. But what's a good way to, say, machine holes in the
stuff? I did a motion-control thing (a magnetic field mapper) on a big
slab of granite, and that was bad enough.
If diamond goes cheap, big blocks of the stuff - silicon-on-diamond;
or at least the back plane of the chip package. Big heat spreader
brazed to the base of your heatsink.
Isotopically pure diamond would have a thermal conductivity/dielectric
constant ratio about 400:1 better than, say, BeO; makes me salivate
just thinking about it.
Let me know when you have samples available.
It's completely speculative at this point. Experimental reduction to
practice is finally straightforward. Our rational target is
abrasive. Cheap diamond dust fill for thermally conductive epoxy
might be attractive. Growing diamond by chemical synthesis out of
molten salt has a potential yield in excess of one carat/hr-cm^2.
Imagine a meter^2 sheet lowered into a vat. 24 hrs later you pull out
100 kg of diamond (both sides plus edges). Even if it is only
abrasive it beats the heck out of any other process - material
throughput, energy costs. So, we'll look.
Bulk carburundum synthesis is not any good for Moissanite gems. Our
process might never threaten de Beers. "8^>)
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
.
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| User: "Mark Thorson" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
09 May 2004 06:57:05 PM |
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John Larkin wrote:
Once we do have slabs of diamond in the McMaster catalog, how
will we machine it? For semiconductor heat spreaders, all we'd
really need is little blocks of the stuff, maybe no holes at all,
so we could buy standard sizes. But what's a good way to, say,
machine holes in the stuff?
Would >90% diamond be good enough? You can get
epoxy molding compound for plastic-packaged
integrated circuits from Sumitomo Bakelite
that is >90% silica. A diamond-filled polymer can
be cast and cured. It might be machinable.
.
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| User: "John Larkin" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
10 May 2004 01:16:16 AM |
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On 9 May 2004 23:57:05 GMT, Mark Thorson <nospam@sonic.net> wrote:
John Larkin wrote:
Once we do have slabs of diamond in the McMaster catalog, how
will we machine it? For semiconductor heat spreaders, all we'd
really need is little blocks of the stuff, maybe no holes at all,
so we could buy standard sizes. But what's a good way to, say,
machine holes in the stuff?
Would >90% diamond be good enough? You can get
epoxy molding compound for plastic-packaged
integrated circuits from Sumitomo Bakelite
that is >90% silica. A diamond-filled polymer can
be cast and cured. It might be machinable.
Filled epoxies aren't especially good thermal conductors and, unless
the particle size is really small, they enforce a gap that wrecks
thermal performance. The value of chunky monochrystalline diamond
would be as a heat spreader between a chip and the main aluminum or
copper heat sink. Sub-50 nm CMOS chips will probably have outrageous
power densities, and the hotter they run the slower they run.
Right now, about the best you can do (dry) is to use a solid copper
heat sink, machined very flat, and clamp the IC package down with a
bit of silicone grease in the gap. You'd probably do the same if the
heatsink were diamond, unless the silicon were truly bonded to the
diamond somehow.
The nano-channel air-cooling thing (as mentioned in another post here)
seems preposterous to me, another case of wild extrapolation without a
hint of calculation.
Seems like, in the end, all problems are thermal problems.
John
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| User: "Uncle Al" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
10 May 2004 11:00:31 AM |
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John Larkin wrote:
On 9 May 2004 23:57:05 GMT, Mark Thorson <nospam@sonic.net> wrote:
John Larkin wrote:
Once we do have slabs of diamond in the McMaster catalog, how
will we machine it? For semiconductor heat spreaders, all we'd
really need is little blocks of the stuff, maybe no holes at all,
so we could buy standard sizes. But what's a good way to, say,
machine holes in the stuff?
Would >90% diamond be good enough? You can get
epoxy molding compound for plastic-packaged
integrated circuits from Sumitomo Bakelite
that is >90% silica. A diamond-filled polymer can
be cast and cured. It might be machinable.
Filled epoxies aren't especially good thermal conductors and, unless
the particle size is really small, they enforce a gap that wrecks
thermal performance. The value of chunky monochrystalline diamond
would be as a heat spreader between a chip and the main aluminum or
copper heat sink. Sub-50 nm CMOS chips will probably have outrageous
power densities, and the hotter they run the slower they run.
Right now, about the best you can do (dry) is to use a solid copper
heat sink, machined very flat, and clamp the IC package down with a
bit of silicone grease in the gap. You'd probably do the same if the
heatsink were diamond, unless the silicon were truly bonded to the
diamond somehow.
The nano-channel air-cooling thing (as mentioned in another post here)
seems preposterous to me, another case of wild extrapolation without a
hint of calculation.
Seems like, in the end, all problems are thermal problems.
The thermal density of future chips is appalling. We are staring down
100+ watts in an area the size of a postage stamp. The damning volume
is the millimeter or two between the chip and its thermal sink. You
need a heat spreader (diamond; or Moissanite as less good, less
expensive fallback), a cold plate, and a way to get rid of all that
heat.
Frank refrigeration (FREON!) works, but that is adding 300-500 watts
to your box plus the noise. Peltier coolers work, but you would
conservatively need 4X refrigeration power, and two or three stages
multiplying that, and you'd have to dump (way more!) Peltier heat.
Water + antifreeze is marginal (viscosity), and you are back to the
refrigerator. Or plumb the CPU package itself and blow through cold
Freon, or make it the inside of a heat pipe. This is potentially
tough on the leads from turbulence and summed mechanical trauma.
Enviro-whiner hydrochlorofluorocarbons instead of a Freon would give
you a MTBF of about 6 months from corrosion, and the stuff is
intensely tumorigenic by inhalation.
Now worry mismatched thermal coefficients of expansion and condensing
moisture in humid climates. A kilowatt box left on 24/7 gets
expensive.
A solid or sintered diamond package gets you at least 4X the thermal
conductivity of copper. Silicon-on-diamond would be grand if clean
monocrystal slabs of diamond were cheaply available. Diamond dust
wholesales for about $(US)1/gram. If it dropped by a factor of 100,
$10/kg, it would edge into being attractive. Processed sheets of
diamond a millimeter or two thick at less than $1/cm^2 would be nice.
We need a rapid, economic route to synthesize bulk diamond. CPUs to
monster travelling wave tube amplifiers, bulk monocrystal diamond is
the stuff of an advanced civilization. Arguments about the gem
market are small stuff by comparision.
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
.
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| User: "John Larkin" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
11 May 2004 12:07:53 AM |
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On 10 May 2004 16:00:31 GMT, Uncle Al <UncleAl0@hate.spam.net> wrote:
A solid or sintered diamond package gets you at least 4X the thermal
conductivity of copper. Silicon-on-diamond would be grand if clean
monocrystal slabs of diamond were cheaply available. Diamond dust
wholesales for about $(US)1/gram. If it dropped by a factor of 100,
$10/kg, it would edge into being attractive. Processed sheets of
diamond a millimeter or two thick at less than $1/cm^2 would be nice.
"Thin heat spreader" is sort of an oxymoron, no? What we need is a
cube or cylinder of diamond embedded in a copper heatsink, to spread
the heat laterally.
John
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| User: "Gordon D. Pusch" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
11 May 2004 12:15:04 AM |
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Uncle Al <UncleAl0@hate.spam.net> writes:
The thermal density of future chips is appalling. We are staring down
100+ watts in an area the size of a postage stamp. The damning volume
is the millimeter or two between the chip and its thermal sink.
You need a heat spreader (diamond; or Moissanite as less good, less
expensive fallback), a cold plate, and a way to get rid of all that heat.
As I've noted earlier, a =FAR= better solution is to simply start using
reversible logic. The only computing operations that _have_ to generate
heat are the I/O operations.
Furthermore, even using CMOS logic, substantial opportunities for reducing
the heat that is dissipated exist (for example, google on "hot-clock seitz").
An excellent set of lecture notes on reduced energy-dissipation computing
may be found at: <http://www.cs.caltech.edu/~cs181/97-98/181a/lectures/14.ps>.
Molecular electronics will almost certainly have to use mostly or entirely
reversible logic to avoid cooking itself. Nanotech will likewise almost
certainly have to use reversible logic. (Note to Drexlerians: "Rod logic"
is =NOT= reversible, and I do not see a particularly rosy future for it.)
Quantum computers must _NECESSARILY_ be reversible, since irreversiblity
would violate the unitarity of the q-comp's evolution operator.
Additional references on reversible computing, including its relevance to
nanotech:
<http://www.cise.ufl.edu/~mpf/rc/home.html>
<http://www.cise.ufl.edu/research/revcomp/writing.html>
-- Gordon D. Pusch
perl -e '$_ = "gdpusch\@NO.xnet.SPAM.com\n"; s/NO\.//; s/SPAM\.//; print;'
.
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| User: "Robert V Hill" |
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| Title: Re: Scaling beyond 130nm dead or alive? |
21 May 2004 03:22:00 PM |
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Diamond and other material advancement are the way to go. Reversible logic
will solve almost 0% of the heat problems in todays CPUs. Most heat build up
in CPU is leakage, not bit creation. Ideally we would want to build A CPU
with 0 leakage. Once we can do that and heat is still a problem then we will
have to move to Reversible logic.
"Gordon D. Pusch" <g_d_pusch_remove_underscores@xnet.com> wrote in message
news:c7pngo01rfn@enews1.newsguy.com...
Uncle Al <UncleAl0@hate.spam.net> writes:
The thermal density of future chips is appalling. We are staring down
100+ watts in an area the size of a postage stamp. The damning volume
is the millimeter or two between the chip and its thermal sink.
You need a heat spreader (diamond; or Moissanite as less good, less
expensive fallback), a cold plate, and a way to get rid of all that
heat.
As I've noted earlier, a =FAR= better solution is to simply start using
reversible logic. The only computing operations that _have_ to generate
heat are the I/O operations.
Furthermore, even using CMOS logic, substantial opportunities for reducing
the heat that is dissipated exist (for example, google on "hot-clock
seitz").
An excellent set of lecture notes on reduced energy-dissipation computing
may be found at:
<http://www.cs.caltech.edu/~cs181/97-98/181a/lectures/14.ps>.
Diamond and other matirol
.
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| User: "Uncle Al" |
|
| Title: Re: Scaling beyond 130nm dead or alive? |
21 May 2004 05:29:25 PM |
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Robert V Hill wrote:
Diamond and other material advancement are the way to go. Reversible logic
will solve almost 0% of the heat problems in todays CPUs. Most heat build up
in CPU is leakage, not bit creation. Ideally we would want to build A CPU
with 0 leakage. Once we can do that and heat is still a problem then we will
have to move to Reversible logic.
Nobody can make electrically usable n-doped diamond. Anyone who can
will have a key patent on the future. I'm a little surprised all the
folks looking at lithium, nitrogen, and phosphorus dopants have not
considered magnesium or titanium. One doe well to address the new
problem, not old solutions to other problems.
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
.
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| User: "Biff Bubster" |
|
| Title: Re: Scaling beyond 130nm dead or alive? - n type diamond |
12 Jun 2004 10:43:16 AM |
|
|
Uncle Al <UncleAl0@hate.spam.net> wrote in message
news:<c8lvs502mhd@enews3.newsguy.com>...
Robert V Hill wrote:
Diamond and other material advancement are the way to go. Reversible logic
will solve almost 0% of the heat problems in todays CPUs. Most heat build up
in CPU is leakage, not bit creation. Ideally we would want to build A CPU
with 0 leakage. Once we can do that and heat is still a problem then we will
have to move to Reversible logic.
Nobody can make electrically usable n-doped diamond. Anyone who can
will have a key patent on the future. I'm a little surprised all the
folks looking at lithium, nitrogen, and phosphorus dopants have not
considered magnesium or titanium. One doe well to address the new
problem, not old solutions to other problems.
N-type diamond is a difficult problem and confuses a lot of people.
Here are the design requirements:
a) Must be a substitutional dopant.
b) Must be shallow.
The physics behind boron and nitrogen doping of diamond is that they
have NEGATIVE energies of incorporation into the diamond lattice. In
other words it is energetically favorable to replace a carbon atom
with a nitrogen or boron atom. The host lattice will not be strained.
In the past, various clowns have tried other materials and reported
their results in Applied Physics Letters Science etc. The problem is
that because these other atoms are in some sense larger than carbon
when inserted in the diamond lattice they have positive energies of
incorporation and thus either deform the host sites and/or are not
substitutional. When experimenters measure n-type behavior in diamond,
what they are seeing is n-type behavior of the defects created.
Usually, no mobility measurements are reported. Low mobilities usually
confirm this. One could introduce a dopant that engineers a high
mobility n-type defect but that is another story and almost an
oxymoron.
Finally in regards to magnesium and titanium, any potential dopant
needs some surface mobility during growth. Since Mg and Ti form
carbides, (Ti an especially strong one) I have a feeling above a
certain doping level that they will form inclusions similar to V in
SiC. If Mg and Ti don't fit in the diamond lattice and have zero
surface mobility during epitaxy all you will create IMHO is carbide
inclusions in the diamond
.
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| User: "Uncle Al" |
|
| Title: Re: Scaling beyond 130nm dead or alive? - n type diamond |
12 Jun 2004 04:34:15 PM |
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|
Biff Bubster wrote:
Uncle Al <UncleAl0@hate.spam.net> wrote in message
news:<c8lvs502mhd@enews3.newsguy.com>...
Robert V Hill wrote:
Diamond and other material advancement are the way to go. Reversible logic
will solve almost 0% of the heat problems in todays CPUs. Most heat build
up
in CPU is leakage, not bit creation. Ideally we would want to build A CPU
with 0 leakage. Once we can do that and heat is still a problem then we
will
have to move to Reversible logic.
Nobody can make electrically usable n-doped diamond. Anyone who can
will have a key patent on the future. I'm a little surprised all the
folks looking at lithium, nitrogen, and phosphorus dopants have not
considered magnesium or titanium. One doe well to address the new
problem, not old solutions to other problems.
N-type diamond is a difficult problem and confuses a lot of people.
Here are the design requirements:
a) Must be a substitutional dopant.
b) Must be shallow.
The physics behind boron and nitrogen doping of diamond is that they
have NEGATIVE energies of incorporation into the diamond lattice. In
other words it is energetically favorable to replace a carbon atom
with a nitrogen or boron atom. The host lattice will not be strained.
In the past, various clowns have tried other materials and reported
their results in Applied Physics Letters Science etc. The problem is
that because these other atoms are in some sense larger than carbon
when inserted in the diamond lattice they have positive energies of
incorporation and thus either deform the host sites and/or are not
substitutional. When experimenters measure n-type behavior in diamond,
what they are seeing is n-type behavior of the defects created.
Usually, no mobility measurements are reported. Low mobilities usually
confirm this. One could introduce a dopant that engineers a high
mobility n-type defect but that is another story and almost an
oxymoron.
Finally in regards to magnesium and titanium, any potential dopant
needs some surface mobility during growth. Since Mg and Ti form
carbides, (Ti an especially strong one) I have a feeling above a
certain doping level that they will form inclusions similar to V in
SiC. If Mg and Ti don't fit in the diamond lattice and have zero
surface mobility during epitaxy all you will create IMHO is carbide
inclusions in the diamond
Well put! Good research but not optimistic technology. Titanium's
multiple valence states and strong bonding to hydrogen suggest it is
rather more optimistic than you expect in a CVD (e.g., volatile
titanium alkyls, alkoxides, bulky acacs, or titanocene derivatives as
plasma dopants) or equivalent environment. Incorporation of titanium
hydride in short duration HPHT diamond synthesis (or annealing of
existing diamond in geodynamic conditions re Novatek in Utah) would be
an interesting experiment. Aluminum getter in the solvent alloy to
remove nitrogen - though titanium may do that as well.
Titanium can be a very small atom in an appropriate lattice electronic
environment. It's an unlikely n-dopant but not impossible.
The difference between true n-dopants for diamond and induced lattice
defects as n-dopant centers is a critical observation. The vast bulk
of n-doped diamond electronics literature is grandiloquent bombastic
ivory tower swill - all of it predicting a wonderful future of CPUs
cooking at 400 C and loving it. Dielectrics and wiring therein wll be
the subject of further studies.
1) Obtain sustrate.
2) Accelerated ion-bombard.
3) Thermally anneal.
4) Make measurements.
5) Publish.
If only the Periodic Table had more entries.
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
.
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| User: "Fleetie" |
|
| Title: Re: Scaling beyond 130nm dead or alive? - n type diamond |
14 Jun 2004 12:37:34 AM |
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|
"Uncle Al" <UncleAl0@hate.spam.net> wrote
grandiloquent
Amazing! This guy never fails to impress!
Martin
--
M.A.Poyser Tel.: 07967 110890
Manchester, U.K. http://www.fleetie.demon.co.uk
.
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| User: "Biff Bubster" |
|
| Title: Re: Scaling beyond 130nm dead or alive? - n type diamond |
02 Jul 2004 10:46:54 AM |
|
|
Uncle Al <UncleAl0@hate.spam.net> wrote in message
news:<cafssn0tgs@enews4.newsguy.com>...
Biff Bubster wrote:
Uncle Al <UncleAl0@hate.spam.net> wrote in message
news:<c8lvs502mhd@enews3.newsguy.com>...
Robert V Hill wrote:
Diamond and other material advancement are the way to go. Reversible
logic
will solve almost 0% of the heat problems in todays CPUs. Most heat
build
up
in CPU is leakage, not bit creation. Ideally we would want to build A
CPU
with 0 leakage. Once we can do that and heat is still a problem then we
will
have to move to Reversible logic.
Nobody can make electrically usable n-doped diamond. Anyone who can
will have a key patent on the future. I'm a little surprised all the
folks looking at lithium, nitrogen, and phosphorus dopants have not
considered magnesium or titanium. One doe well to address the new
problem, not old solutions to other problems.
N-type diamond is a difficult problem and confuses a lot of people.
Here are the design requirements:
a) Must be a substitutional dopant.
b) Must be shallow.
The physics behind boron and nitrogen doping of diamond is that they
have NEGATIVE energies of incorporation into the diamond lattice. In
other words it is energetically favorable to replace a carbon atom
with a nitrogen or boron atom. The host lattice will not be strained.
In the past, various clowns have tried other materials and reported
their results in Applied Physics Letters Science etc. The problem is
that because these other atoms are in some sense larger than carbon
when inserted in the diamond lattice they have positive energies of
incorporation and thus either deform the host sites and/or are not
substitutional. When experimenters measure n-type behavior in diamond,
what they are seeing is n-type behavior of the defects created.
Usually, no mobility measurements are reported. Low mobilities usually
confirm this. One could introduce a dopant that engineers a high
mobility n-type defect but that is another story and almost an
oxymoron.
Finally in regards to magnesium and titanium, any potential dopant
needs some surface mobility during growth. Since Mg and Ti form
carbides, (Ti an especially strong one) I have a feeling above a
certain doping level that they will form inclusions similar to V in
SiC. If Mg and Ti don't fit in the diamond lattice and have zero
surface mobility during epitaxy all you will create IMHO is carbide
inclusions in the diamond
Well put! Good research but not optimistic technology. Titanium's
multiple valence states and strong bonding to hydrogen suggest it is
rather more optimistic than you expect in a CVD (e.g., volatile
titanium alkyls, alkoxides, bulky acacs, or titanocene derivatives as
plasma dopants) or equivalent environment. Incorporation of titanium
hydride in short duration HPHT diamond synthesis (or annealing of
existing diamond in geodynamic conditions re Novatek in Utah) would be
an interesting experiment. Aluminum getter in the solvent alloy to
remove nitrogen - though titanium may do that as well.
Titanium can be a very small atom in an appropriate lattice electronic
environment. It's an unlikely n-dopant but not impossible.
The difference between true n-dopants for diamond and induced lattice
defects as n-dopant centers is a critical observation. The vast bulk
of n-doped diamond electronics literature is grandiloquent bombastic
ivory tower swill - all of it predicting a wonderful future of CPUs
cooking at 400 C and loving it. Dielectrics and wiring therein wll be
the subject of further studies.
1) Obtain sustrate.
2) Accelerated ion-bombard.
3) Thermally anneal.
4) Make measurements.
5) Publish.
If only the Periodic Table had more entries.
You have indirectly alluded to the one way to make bipolar diamond
devices, high temperatures. If I recall correctly there was an APL
paper demonstrating a high temperature bipolar PN diode using an
p-type(boron) homoepi layer grown on an HPHT Sumitomo nitrogen doped
diamond substrate. The temperature of the device was +500C. The
results were decent, but at such high tempertures you run into another
problem which is carrier mobilities. At room temperature hole
mobilities are hugh, but no n-type substitutional dopant and at the
temperatures where nitrogen starts contributing electrons the mobility
drops.
.
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| User: "Uncle Al" |
|
| Title: Re: Scaling beyond 130nm dead or alive? - n type diamond |
02 Jul 2004 12:16:04 PM |
|
|
Biff Bubster wrote:
Uncle Al <UncleAl0@hate.spam.net> wrote in message
news:<cafssn0tgs@enews4.newsguy.com>...
Biff Bubster wrote:
Uncle Al <UncleAl0@hate.spam.net> wrote in message
news:<c8lvs502mhd@enews3.newsguy.com>...
Robert V Hill wrote:
[snip]
N-type diamond is a difficult problem and confuses a lot of people.
Here are the design requirements:
a) Must be a substitutional dopant.
b) Must be shallow.
The physics behind boron and nitrogen doping of diamond is that they
have NEGATIVE energies of incorporation into the diamond lattice. In
other words it is energetically favorable to replace a carbon atom
with a nitrogen or boron atom. The host lattice will not be strained.
In the past, various clowns have tried other materials and reported
their results in Applied Physics Letters Science etc. The problem is
that because these other atoms are in some sense larger than carbon
when inserted in the diamond lattice they have positive energies of
incorporation and thus either deform the host sites and/or are not
substitutional. When experimenters measure n-type behavior in diamond,
what they are seeing is n-type behavior of the defects created.
Usually, no mobility measurements are reported. Low mobilities usually
confirm this. One could introduce a dopant that engineers a high
mobility n-type defect but that is another story and almost an
oxymoron.
[snip]
The difference between true n-dopants for diamond and induced lattice
defects as n-dopant centers is a critical observation. The vast bulk
of n-doped diamond electronics literature is grandiloquent bombastic
ivory tower swill - all of it predicting a wonderful future of CPUs
cooking at 400 C and loving it. Dielectrics and wiring therein wll be
the subject of further studies.
1) Obtain sustrate.
2) Accelerated ion-bombard.
3) Thermally anneal.
4) Make measurements.
5) Publish.
If only the Periodic Table had more entries.
You have indirectly alluded to the one way to make bipolar diamond
devices, high temperatures. If I recall correctly there was an APL
paper demonstrating a high temperature bipolar PN diode using an
p-type(boron) homoepi layer grown on an HPHT Sumitomo nitrogen doped
diamond substrate. The temperature of the device was +500C. The
results were decent, but at such high tempertures you run into another
problem which is carrier mobilities. At room temperature hole
mobilities are hugh, but no n-type substitutional dopant and at the
temperatures where nitrogen starts contributing electrons the mobility
drops.
A hot chip has poor MTBF. Metallizations will fail, dopants will
diffuse, differing CTEs will break connections. New small
architecture chips use exotic low epsilon dielectrics instead of
straight SiO2 - fluorinated silica, porous silica, carbon-containing
silica (methyl groups; usually burned out after deposition). They
don't like high temps.
Diamond n-p junctions are demonstrated to work as expected. A usable
n-doped diamond is nowhere near reduction to practice. That suggests
everybody is doing it wrong - one cannot find a needle in a haystack
if it isn't in there. A chemist would then shout "umpolung!" and do
something different. All this work is being pursued by engineers who
will instead "optimize" the response surface. One would do better to
make it the topic of a high school science fair and get some original
thought plus a few goofs in there.
The whole of Zieglar-Natta polyolefin catalysis traces back to a dirty
autoclave. Nobody knows the name of the technican whose sloppy
technique obtained the now $trillion discovery. The discoveries of
saccharin and aspartame were contingent upon chemists accidentally
tasting their work being performed in other venues. In a properly
managed world they would have all been discharged for cause -
incompetence and insubordination - and the inventions rewarded to more
deserving folk adherent to Korporate Kulture.
Uncle Als says, "Discovery does not reside within a PERT chart."
--
Uncle Al
http://www.mazepath.com/uncleal/
(Toxic URL! Unsafe for children and most mammals)
"Quis custodiet ipsos custodes?" The Net!
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